Are you up for the challenge to develop next generation integrated circuits for our continued leadership in mobile communications? In radio base stations, high-speed, time-interleaved, analog-to-digital converters (ADCs) are used to handle wide band signals. In this technique several lower speed sub-ADCs are used in parallel in a time interleaved fashion, so that when N sub-ADCs are used, each sub-ADC only needs to process every N:th sample, hence reducing the speed requirement of each sub-ADC by N times. However, due to mismatch between the sub-ADCs, such as offset in comparators, non-linearities are introduced. In this thesis we want to investigate randomizing and averaging techniques to mitigate these mismatch errors. In short, the average values of all sub-ADCs are used as the reference to which all sub-ADCs are correct. The correction values are stored in N individual look up tables. The thesis incudes both system-, and lower-level simulations.

Thesis Description

The following steps are envisioned as part of the thesis work:

  • Literature survey to find current- and the state-of-the-art solutions.
  • System level modeling in MATLAB
  • Schematic design of critical building blocks and transistor level verification
  • The thesis work will be concluded with a presentation for the Ericsson team.


  • This project aims at students in electrical engineering, computer engineering or similar with interest in full custom integrated circuit design.
  • Analog/digital circuit design basics (relevant coursework).
  • Experience in transistor schematic design (Virtuoso IC) and circuit verification (Spectre simulator).
  • Custom layout design experience (preferred but not mandatory).



1 student, 30hp

Preferred Starting Date

Spring 2024


Ericsson AB Mjärdevi, Linköping


Full custom, ASIC, BIST, CMOS, Data Converters,

Contact Persons

Recruiting Manager

Niklas Andersson                                                                                         Håkan Bengtsson

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